1. Field of the Invention
The present invention relates to a thin film transistor (TFT) and a method for fabricating the same and, more particularly, to a thin film transistor which has an offset region formed in a channel region so as to reduce current leakage which may be generated through the channel region when the TFT is turned OFF, and a method for fabricating the same.
2. Description of the Prior Art
Generally, polysilicon is widely used in manufacturing integrated circuits or semiconductor devices such as TFTs because of its effective switching performance and integration ability. Therefore, when the TFT made of polysilicon is applied to an active matrix liquid crystal display, a drive circuit for driving a pixel of the liquid crystal display and TFTs can be formed on a same substrate.
However, the TFT made of polysilicon has a drawback in that when it is turned OFF, current leakage may occur because of deterioration of the OFF characteristic.
In an effort to overcome this problem, an offset region where impurities are not doped or lightly doped (hereinafter referred to as an "offset region") is formed in a channel region of the TFT so as to reduce the current leakage which flows from a drain region and/or a source region to a gate when the TFT is turned OFF.
FIG. 5 shows a conventional TFT in which a gate electrode is made of polysilicon.
A buffer layer 2 is first formed on a substrate 1, after which an active layer forming material such as polysilicon is deposited on the buffer layer 2. Next, the active layer forming material is etched through a photolithography process, thereby forming an active layer 3 on the buffer layer 2. A gate oxide layer 4 is deposited on the active layer 3, after which a gate electrode forming material such as a polysilicon is deposited on the gate oxide layer 4, then etched through a photolithography process, thereby forming a gate electrode 5.
Following the above, impurities are lightly doped in the active layer 3 using the gate electrode 5 as a mask. Next, the gate electrode 5 is heat-treated at a high temperature so that an oxide layer 6 is formed on a surface of the gate electrode 5, after which impurities are heavily doped in the active layer 3 using the oxide layer 6 as a mask.
As a result, a portion of the active layer 3 corresponding to the oxide layer 6 becomes an offset region II where the impurities are lightly doped, while other portions of the active layer 3 becomes a source/drain region 3a where the impurities are heavily doped. That is, the active layer 3 comprises a channel region I where the impurities are not doped, the lightly doped offset region II, and the source/drain region 3a through which electric signals are applied.
In the above described structure, since the source/drain region 3a is spaced away from the gate electrode 5 by the offset region II, an electric field effect from source and drain terminals having a predetermined electric potential to the gate electrode 5 is reduced. As a result, when the TFT is turned OFF, current leakage between the source and drain terminals is reduced, thereby improving an Off-current characteristic of the TFT.
However, in the TFT structured as in the above, heat treating the gate electrode to form the oxide layer may deform the substrate, deteriorating a reliability of the resultant TFT. In addition, during the heat treatment process, the impurities lightly doped in the active layer may be activated, making it difficult to form a precise profile. When the polysilicon used for the gate electrode has a high resistance, the TFT made of the polysilicon cannot be applied to a large-sized liquid crystal display.
Therefore, to overcome the above drawbacks, there is disclosed a conventional method for forming the gate electrode using metal.
FIG. 6 shows a conventional TFT in which a gate electrode is made of a metal.
A buffer layer 2 is first formed on a substrate 1, after which an active layer forming material such as a polysilicon is deposited on the buffer layer 2. Next, the active layer forming material is etched through a photolithography process, thereby forming an active layer 3 on the buffer layer 2. A gate oxide layer 4 is deposited on the active layer 3, after which a gate electrode forming material such as metal is deposited on the gate oxide layer 4, then etched through a photolithography process, thereby forming a metal gate electrode 7.
Following the above, impurities are lightly doped in the active layer 3 using the metal gate electrode 7 as a mask. Next, a photoresist pattern PR is formed around the metal gate electrode 7, after which impurities are heavily doped in the active material 3 using the photoresist pattern PR as a mask.
As a result, a portion of the active layer 3 corresponding to the photoresist pattern PR becomes an offset region II where the impurities are lightly doped, while other portions of the active layer 3 becomes a source/drain region 3a where the impurities are heavily doped. That is, the active layer 3 comprises a channel region I where the impurities are not doped, the lightly doped offset region II, and the heavily doped source/drain region 3a through which electric signals are applied.
However, in the above described method, the additional masking process for forming the photoresist pattern around the metal gate electrode makes the overall process for making the TFT complicated.